An integrated circuit (IC) die may be attached, both mechanically and electrically, to a package substrate. The IC die may have an array of bond pads on the die's “front” side, and a solder bump or other lead may be affixed to each of these bond pads. A mating array of lands is disposed on the package substrate, and the die is placed face down on the substrate such that the array of solder bumps extending from the die are aligned with the mating array of lands on the substrate. The solder bumps extending from the IC die are then coupled to their respective lands on the substrate. The package substrate may include multiple layers of conductors (e.g., traces), and these conductors can route electrical signals (running to and from the die) to locations on the package substrate where electrical connections can be established with a next-level component (e.g., a motherboard, a computer system, a circuit board, another IC device, etc.). For example, the substrate circuitry may route all signal lines to a ball-grid array (or, alternatively, a pin-grid array) formed on a lower surface of the package substrate, and this ball- or pin-grid array then electrically couples the packaged IC die to the next-level component, which includes a mating array of terminals (e.g., lands, pin sockets, etc.). The use of an array of solder bumps (or columns, etc.) to couple an IC die to a substrate is often referred to as Controlled Collapse Chip Connect (or C4).
As noted above, an array of solder bumps extends from the front side of the IC die—each of these solder bumps being coupled with a bond pad on the die—and these solder bumps are coupled with a mating array of lands on the package substrate. To couple these solder bumps to the mating array of substrate lands, the assembly (e.g., die and substrate) may be placed in an oven and heated to reflow the solder bumps. For lead-based solder compositions, the reflow temperature may be approximately 225 degrees Celsius, and for lead-free solder compositions the reflow temperature may be approximately 260 degrees Celsius. Upon solidification of the solder bumps, an electrical and mechanical bond is formed between the solder bumps and their mating lands on the package substrate.
During solder reflow, both the die and substrate may be heated to the reflow temperature, which can lead to thermal expansion of these components. However, the coefficient of thermal expansion (CTE) of the IC die may be substantially different than the CTE of the package substrate. For example, a die made of silicon will have a CTE of approximately 3 ppm/° C., whereas an organic substrate may have a CTE of approximately 16 ppm/° C. Upon cool down after reflow, the reflowed solder bumps solidify to form solid interconnects between the die and substrate. At the same time, due to the difference in CTE between the IC die and package substrate, a differential thermal displacement occurs between the die and substrate. Because of this differential thermal displacement, as well as the mechanical stiffness of the solid interconnects that are formed, significant residual stresses may develop. These residual stress may impact both the IC die (e.g., the die's interconnect structure) and the package substrate, as well as the solder interconnects extending between these two components. These residual stresses may, for example, result in die warpage as well as cracking of the die's interconnect structure. The IC die's interconnect structure may be formed from a low-k dielectric material—which generally has lower mechanical strength in comparison to materials having a higher dielectric constant—and an interconnect structure formed from these low-k dielectric materials may be especially sensitive to cracking as a result of the above-described differential thermal displacement.